Semiconductor chips commonly incorporate myriad electronic elements such as transistors, capacitors, resistors and the like, together with more complex electronic elements such as logic gates, amplifiers, comparators, and many other passive and active electrical components. These elements typically are provided in one or more layers extending parallel to the front and back surfaces of the chip. The various electronic elements of the chip typically are interconnected with one another by metallic traces extending within the chip in the horizontal or xe2x80x9cXxe2x80x9d and xe2x80x9cYxe2x80x9d directions and metallic vias extending in the vertical or xe2x80x9cZxe2x80x9d direction. Typically, the traces and vias are formed of conductive material deposited during fabrication of the chip as, for example, aluminum or polysilicon. The traces and vias used to interconnect the electronic elements of the chip with one another complicate design and fabrication of the chip.
Moreover, the traces which are fabricated during manufacture of the chip do not always provide optimum electrical characteristics. For example, the traces typically are formed from aluminum, which has a relatively high resistivity. Although processes for fabricating traces in a chip from low-resistivity metals such as copper are known, these processes impose special requirements in chip fabrication. Further, even if a low-resistivity metal is employed, the size and hence the cross-sectional area of traces which can be accommodated within a chip are subject to severe limitations. Traces extending within a chip often follow indirect routes because other elements of the chip lie in a direct route between the electronic elements connected by the trace.
Additionally, chips must be connected to external circuit elements. In the conventional approach to chip packaging, each chip is incorporated in a separate package bearing leads or other external connecting elements. Contacts on the surface of the chip are connected to these external connecting elements. The external connecting elements on the package are connected to a conventional circuit board or other circuit-bearing substrate. Alternatively, several chips may be mounted in a single package, commonly referred to as a xe2x80x9cmultichip module.xe2x80x9d These chips may be connected to one another and to a common set of external connecting elements, so that the entire assembly can be mounted to the substrate as a unit. In yet another alternative, the chip itself is attached directly to the substrate.
As described in Arima et al., U.S. Pat. No. 5,281,151, a package in the form of a rigid ceramic board may be provided with a set of xe2x80x9cthin filmxe2x80x9d circuit layers overlying the ceramic board. The thin film layers include metallic traces on a material such as polyimide which has a relatively low dielectric constant. A chip is mounted to the thin film layers by solder balls in engagement with contacts on the chip. A signal can be routed from point to point within the chip along a signal path through a solder ball at one location on the chip, along a metallic trace of the thin film element and back into the chip through a solder ball at another location on the chip. The thin film layer assertedly provides low resistance and relatively rapid signal transmission between elements of the chip.
As described in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390, 5,518,964 and the corresponding WO 96/02068 published Jan. 25, 1996, as well as in co-pending, commonly assigned U.S. patent applications Ser. No. 08/653,016, filed May 24, 1996, now U.S. Pat. Nos. 5,688,716; 08/678,808 filed Jul. 12, 1996 as well as 08/532,528 filed Sep. 22, 1995, and the corresponding International Publication No. WO 97/11486 published Mar. 27, 1997, the disclosures of which are all incorporated by reference herein, it is desirable to provide interconnections between the contacts on a chip and external circuitry by providing a further dielectric element, which may be referred to as a xe2x80x9cinterposerxe2x80x9d or xe2x80x9cchip carrierxe2x80x9d having terminals. Terminals on the dielectric element are connected to the contacts on the chip by flexible leads. The terminals on the dielectric element may be connected to the substrate as, for example, by solder bonding the terminals to contact pads of the substrate. The dielectric element remains movable with respect to the chip so as to compensate for thermal expansion and contraction of the components. That is, various parts of the chip can move with respect to the dielectric element as the chip grows and shrinks during changes in temperature. In a particularly preferred arrangement, a compliant dielectric layer is provided as a separate component so that the compliant layer lies between the chip and the terminals. The compliant layer may be formed from a soft material such as a gel, elastomer, foam or the like. The compliant layer mechanically decouples the dielectric element and terminals from the chip and facilitates movement of the dielectric element relative to the chip. The compliant layer may also permit movement of the terminals in the Z direction, towards the chip, which further facilitates testing and mounting of the assembly.
As disclosed in copending, commonly assigned U.S. patent application Ser. No. 08/641,698, and International Publication No. WO 97/40958 the disclosure of which is also incorporated by reference herein, the electrically conductive parts on the dielectric element may be connected to the chip by masses of a fusible, electrically conductive material which is adapted to melt at temperatures encountered during processing or operation of the assembly. These masses may be constrained by a surrounding compliant dielectric material so that they remain coherent while in a molten state. The molten masses provide another form of deformable conductive element, which allows movement of the flexible dielectric element relative to chip. As further disclosed in commonly assigned patents and patent applications, one or more chips may be mounted to a common dielectric element or interposer, and additional circuit elements also may be connected to such a dielectric element. The dielectric element may incorporate conductive traces which form interconnections between the various chips and electronic components of the assembly.
Designers of multichip modules have provided connections between different chips as transmission lines including plural conductors. As discussed in Multichip Module Technologies and Alternativesxe2x80x94The Basics, Doane and Franzon, eds., Chapter 11, pp. 525-568, Electrical Design of Multichip Modules (1993), a signal line extending between a pair of digital elements on different chips of a module may extend over a reference plane, such as a ground or power plane, so that the signal line, reference plane and intervening dielectric constitute a controlled-impedance transmission line.
Despite all of these efforts in the art, however, there are significant needs for improvements in semiconductor chips and assemblies incorporating the same. In particular, there are needs for improved chip assemblies which can provide rapid and reliable propagation of signals between electrical elements within a single chip.
The present invention addresses these needs.
A microelectronic assembly in accordance with one aspect of the present invention incorporates a first semiconductor chip including a plurality of electronic elements adapted to receive and send signals. The electronic elements of the chip may include any of the electronic components mentioned above and any other types which may incorporated in a chip. The chip includes a front surface having contacts thereon. At least some of the electronic elements are connected to the contacts. The assembly further includes a dielectric element separate from the chip. The dielectric element has a plurality of conductive interconnect traces on it.
Most preferably, the dielectric element is movable with respect to the chip. In this case, the assembly includes a plurality of deformable conductive elements such as fusible masses which are at least partially liquid at the operating temperature of the chip or, preferably, flexible leads extending between the chip and the dielectric element. The deformable conductive elements interconnect at least some of the contacts on the chip with at least some of the traces so that at least some of the active electronic elements in the first semiconductor chip are connected to one another for transmission of signals therebetween through the deformable conductive elements and the interconnect traces on the dielectric element. Preferably, a compliant material is provided between the chip and the dielectric element to provide mechanical decoupling between the chip and the dielectric element.
In the preferred assemblies according to this aspect of the invention, signals travel between electronic elements of a single chip through the traces on a separate dielectric element which remains movable with respect to the chip. The dielectric element can have a coefficient of thermal expansion different from that of the chip. The deformable conductive elements will compensate for movement of the traces relative to the contacts on the chip. The ability to use a dielectric element having a coefficient of expansion different from that of the chip allows the designer to use dielectric layers such as polyimide layers with substantial copper features. Structures of this type have electrical properties such as high conductivity and relatively low dielectric constant, but have thermal expansion properties close to those of copper and significantly different from those of the chip.
The dielectric element may be a flat element such as a platelike or sheetlike element having a bottom surface and a top surface opposite from the bottom surface. Most preferably, the dielectric element includes a flexible polymeric sheet or a laminate including plural sheets, having one or more layers of interconnect traces thereon. Where the dielectric element is a flat plate or sheet, the interconnect traces generally will extend in horizontal directions, parallel to the top and bottom surfaces of the dielectric element.
According to a further aspect of the invention, a semiconductor chip assembly includes a first semiconductor chip as aforesaid and a dielectric element separate from the chip. The dielectric element has a plurality of conductive features thereon. At least some of said contacts are connected with at least some of the conductive features so that at least some of the electronic elements of the chip are connected to one another by the conductive features. The conductive features on the dielectric element include at least one set of plural conductive features defining a multiconductor transmission line extending between spaced-apart locations on the dielectric element. The electronic elements of the chip include at least one pair of multiply-connected elements, each said pair of multiply-connected elements is connected to one another through the plural conductive features of one said transmission line.
For example, the conductive features of the dielectric element may include interconnect traces as aforesaid and conductive potential reference elements such as substantially continuous electrically-conductive potential planes. The interconnect traces may be arranged in layers so that some or all of the trace layers are juxtaposed with potential planes. Thus, the traces in these layers are juxtaposed with the potential planes so that each trace and the adjacent potential plane forms a transmission line of the type commonly referred to as a stripline. In such an arrangement, one potential plane may serve as a part of several transmission lines. Alternatively or additionally, the conductive features on the dielectric element may include sets of traces extending adjacent one another, such as two or three traces extending alongside one another. The traces of each such set may define a single multiconductor transmission line. The transmission line configurations discussed above minimize crosstalk between different signals and reduce susceptibility to electromagnetic interference. Further, the transmission lines preferably provide controlled impedance along the length of the transmission line. Most preferably, the characteristic impedance of the transmission line does not change abruptly at any point along the length of the transmission line. Assemblies according to this aspect of the invention provide rapid propagation of signals between widely separated elements on the chip. The most preferred assemblies take advantage of both aspects of the invention, and hence include multiconductor transmission lines on a dielectric element which is connected to the chip through deformable conductive elements and movable with respect to the chip.
At least some ends of the transmission lines, the conductive features of the transmission line are connected to a multiply-connected element of the chip through a plurality of adjacent contacts on said chip. Ends where such connections are provided are referred to herein as xe2x80x9cadjacent-connectedxe2x80x9d ends of the transmission lines. The deformable conductive elements may include flexible leads connecting the conductive features of each transmission line to the contacts on the chip at each such adjacent-connected end. The flexible leads at each adjacent-connected end may include plural separate flexible leads extending next to one another. The leads may be physically parallel to one another. Most preferably, the leads are curved in horizontal directions parallel to the surface of the chip, and the curved leads are nested within one another. The parallel leads provide an extension of the multiconductor transmission line. The parallel leads desirably provide a characteristic impedance close to the characteristic impedance of the transmission line itself.
Alternatively, the flexible leads at least some of said adjacent-connected ends may include a plural-conductor flexible lead incorporating a plurality of conductors extending next to one another and a dielectric between such conductors. Typically, a single plural-conductor lead provides the sole connection of the stripline to the contacts at an end of the transmission line. Here again, the plural-conductor lead can be impedance-matched to the transmission line.
Typically, the electronic elements of the chip are arranged to send and receive digital signals in synchronism with a common clock, such as the internal clock of the chip itself. As discussed below, the transmission lines provide rapid signal transmission between the elements and thus allow operation of the chip at a high clock speed. The transmission lines on the dielectric element may distribute the clock signal itself. The transmission lines may be provided in a branching pattern with characteristic impedances selected to suppress signal reflections at the branching points.
The dielectric element may be provided with terminals for connection to an external circuit or substrate. For example, the dielectric element desirably overlies the front surface of the chip, so that a bottom surface of the dielectric element faces towards the front or contact-bearing surface of the chip. A compliant layer desirably is disposed between the dielectric element and the chip. Terminals on the dielectric element may be accessible at the top surface of the dielectric element, facing away from the chip. Thus, the terminals may project from the top surface or may be recessed within holes or vias extending into the dielectric element from the top surface. Some or all of the terminals on the dielectric element may be connected to the first chip through the deformable conductive elements, so that the first chip can be connected to an external substrate by connecting the terminals to contact pads on the substrate. In this instance, the dielectric element and deformable conductive elements serve as part of the package for the chip. The assembly may further include a second semiconductor chip having electronic elements therein. The second semiconductor chip also may be juxtaposed with the dielectric element and may be connected to at least some of the traces on the dielectric element. Thus, the traces on the dielectric element may also form interconnections between the first and second chips so as to provide a multichip module. The assembly may further include one or more auxiliary circuit elements such as capacitors or other discrete components juxtaposed with the dielectric element and connected to at least some of the traces. The traces connect the chip or chips to the auxiliary circuit element as well.
Still further aspects of the present invention provide methods of making semiconductor assemblies. Methods according to this aspect of the invention preferably include the step providing a unitary semiconductor structure having a front surface. The semiconductor structure may be a chip or wafer incorporating a plurality of electronic elements within said structure and contacts on the front surface. The electronic elements have signal connections and are adapted to send and receive time-varying signals through these connections. Preferably, the electronic elements also have constant-potential connections such as ground and/or power connections. At least some of the signal connections are connected to the contacts. The method according to this aspect of the invention further includes the step of assembling a dielectric structure having electrically conductive features thereon to said semiconductor structure so as to connect the electrically conductive features with said contacts through deformable conductive elements. The assembling step is performed in such a manner that that signal connections of at least some of the electronic elements within said unitary semiconductor structure are connected to one another through the contacts, the deformable conductive elements and the conductive features on said dielectric structure. The assembling step is also performed in such a manner that the dielectric structure remains movable with respect to said semiconductor structure.
The unitary semiconductor structure may include a plurality of chips. In this case, the assembling step desirably is performed so that electronic elements within each said chip are connected to one another through conductive features within a portion of the dielectric structure associated with that chip. The method may further include the step of severing the unitary semiconductor structure to separate each said chip from the unitary semiconductor structure so that the portion of the dielectric structure associated with such chip remains with the chip.
Methods according to this aspect of the invention can be used to fabricate assemblies as discussed above.